A leadless leadframe can be implemented in semiconductor package with lower cost and smaller dimension. A well-know leadless semiconductor package comprises a semiconductor chip, a leadless metal leadframe for carrying the chip and a package body encapsulating the chip. A plurality of leads of the leadless leadframe has a lower surface exposed out of the bottom of the package body for electrical connection to the outside world. Normally, no outer leads extended from the sidewall of the package body are needed. The leadless semiconductor package is of benefits to smaller dimension, shorter electrical paths, and lower manufacturing cost.
A leadless semiconductor package is disclosed in U.S. Pat. No. 6,143,981. As shown in FIG. 1, the semiconductor package comprises a leadless leadframe 10, a semiconductor chip 20, a plurality of bonding wires 30, and a package body 40. The leadless leadframe 10 comprises a die pad 11 and a plurality of leads 12. The semiconductor chip 20 is attached to an upper surface 11a of the die pad 11. The bonding wires 30 connect bonding pads 21 of the semiconductor chip 20 to the leads 12. The package body 40 encapsulates the semiconductor chip 20. As shown in FIG. 2, it is inevitable that a lower surface 11b of the die pad 11 and the lower surfaces of the leads 12 are exposed out of the bottom surface of the package body 40 for heat dissipation and SMT connection, but leading poor mold locking capability of the die pad 11 and the leads 12 to the package body 40. As shown in FIG. 1, a reentrant portion 13 is formed on the sidewall of the die pad 11 and the leads 12 and is encapsulated by the package body 40 for preventing the die pad 11 peeling off from the package body 40 in vertical direction. However, the reentrant portion 13 is annular design in horizontal direction, therefore, it's unable to enhance the horizontal mold locking of the die pad 11 against the package body 40. Moreover, the coefficients of thermal expansion (CTE) of the die pad 11 and the package body 40 do not match with each other. When the thermal test of the leadless semiconductor package, a horizontal stress is generated between the package body 40 and the die pad 11. The sidewall of the die pad 11 can be delaminated from the package body 40 to slide horizontally. Especially, when the temperature of the leadless semiconductor package is reached up to 260° C. for surface mounting, the sidewall of the die pad 11 will encounter extremely high thermal stress in horizontal direction and then causing delamination from the package body 40.